An engineer designing an integrated circuit can choose from a number of target devices. Two commonly chosen target devices are application-specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs). Typically, ASICs offer better density, performance, and power than FPGAs but require large non-recurring engineering (NRE) costs. FPGAs have much lower NRE costs, but a higher unit cost. So for larger quantities of production, it makes economic sense to produce ASICs rather than FPGAs.
A structured ASIC (or neo-gate-array) is a target device that combines the flexibility of an FPGA with the efficiency of an ASIC. A structured ASIC ordinarily consists of a base array of hard blocks (e.g., I/O and RAM) along with relatively simple logic structures in a regular fabric that is hard-wired for most processing layers, but which can be targeted to a specific application by customizing several (e.g., two to four) metal or via layers. As the technology for structured ASICs has become more mature, a design flow that mitigates risk has emerged which involves the prototyping, testing, and initial shipment of a design using an FPGA and then the migration of that design to a structured ASIC or custom (e.g., full-custom) ASIC for volume production.
Altera Corporation has developed an application program in the field of electronic design automation (EDA) called Quartus®. Among other things, some implementations of Quartus® facilitate the migration between devices (e.g., by constraining the design of the source and/or target device and/or its package) with different resource densities when the devices are in the same family and fit on the same package (e.g., ball grid array). This sort of migration is sometimes referred to as “vertical migration”. Such devices can use the same printed circuit board (PCB). Some implementations of Quartus® also facilitate the migration between devices with different resource densities when the devices are in the same family and the smaller device's resources are a subset of the larger device's resources. This sort of migration is sometimes referred to as “SameFrame migration”. Here again such devices can use the same PCB. Finally in this regard, some implementations of Quartus® facilitate the migration from a design (e.g., die and device package combination) for an FPGA and to a design (e.g., die and device package combination) for a structured ASIC, when the FPGA and the structured ASIC fit onto the same device package and therefore the same PCB. This sort of migration is sometimes referred to as “HardCopy® migration”, where HardCopy® is the name of a structured ASIC developed by Altera Corporation.
As logic (or IP) cores have become smaller, the cost of the device package has increased as a percent of the total cost of a device. Consequently, there exists a need for functionality to facilitate the migration from an FPGA design to a structured ASIC or custom ASIC design that uses a device package that is smaller than the device package used by the FPGA design. The inventions described below include such functionality, along with additional functionality which is widely applicable to this and other fields.